1. Field of the Invention
This invention relates to a ferroelectric memory with respect to a semiconductor memory device.
2. Description of the Related Art
A background ferroelectric memory includes two or more memory cells which have a ferroelectric capacitor and a selection transistor. Each memory cell is provided at a respective intersection of a word line and a bit line. Each memory cell includes one ferroelectric capacitor, and the ferroelectric capacitor stores logical data.
In recent years, miniaturization of a memory chip and high-density of data are increasingly desired. However, in the background ferroelectric memory, each memory cell can store only 1 bit data, unless a ferroelectric capacitor stores multi-value data.